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1. general description the adc1413d is a dual-channel 14-bit analog-to-digital converter (adc) optimized for high dynamic performance and low power at sample rates up to 125 msps. pipelined architecture and output error correction ensure the adc1413d is accurate enough to guarantee zero missing codes over the entire operating range. supplied from a 3 v source for analog and a 1.8 v source for the output driver, it embeds two serial outputs. each lane is differential and complies with the jesd204a standard. an integrated serial peripheral interface (spi) allows the user to easily conf igure the adcs. a set of ic configurations is also available via the binary level control pi ns taken, which are used at power-up. the device also includes a programmable full-scale spi to allow a flexible input voltage range of 1 v to 2 v (peak-to-peak). excellent dynamic performance is maintained from the baseband to input frequencies of 170 mhz or more, making the adc1413d ideal for use in communications, imaging, and medical applications. 2. features and benefits adc1413d series dual 14-bit adc; 65 msps, 80 ms ps, 105 msps or 125 msps; serial jesd204a interface rev. 6 ? 8 june 2011 product data sheet ? snr, 72 dbfs; sfdr, 86 dbc ? input bandwidth, 600 mhz ? sample rate up to 125 msps ? power dissipation, 995 mw at 80 msps ? clock input divided by 2 for less jitter contribution ? spi register programming ? 3 v, 1.8 v power supplies ? duty cycle stabilizer (dcs) ? flexible input volt age range: 1 v (p-p) to 2 v (p-p) ? high if capability ? two configurable serial outputs ? offset binary, two?s complement, gray code ? compliant with jesd204a serial transmission standard ? power-down mode and sleep mode ? pin compatible with the adc1613d series, adc1213d series, and adc1113d125 ? hvqfn56 package
adc1413d_ser all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 6 ? 8 june 2011 2 of 43 nxp semiconductors adc1413d series dual 14-bit adc; serial jesd204a interface 3. applications 4. ordering information ? wireless and wired broadband communications ? portable instrumentation ? spectral analysis ? imaging systems ? ultrasound equipment ? software defined radio table 1. ordering information type number sampling frequency (msps) package name description version adc1413d125hn/c1 125 hvqfn56 plastic therma l enhanced very thin quad flat package; no leads; 56 terminals; body 8 ? 8 ? 0.85 mm sot684-7 adc1413d105hn/c1 105 hvqfn56 plastic therma l enhanced very thin quad flat package; no leads; 56 terminals; body 8 ? 8 ? 0.85 mm sot684-7 ADC1413D080HN/c1 80 hvqfn56 plastic therma l enhanced very thin quad flat package; no leads; 56 terminals; body 8 ? 8 ? 0.85 mm sot684-7 adc1413d065hn/c1 65 hvqfn56 plastic therma l enhanced very thin quad flat package; no leads; 56 terminals; body 8 ? 8 ? 0.85 mm sot684-7
adc1413d_ser all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 6 ? 8 june 2011 3 of 43 nxp semiconductors adc1413d series dual 14-bit adc; serial jesd204a interface 5. block diagram fig 1. block diagram error correction and digital processing clock input stage and duty cycle control adc a core 14-bit pipelined t/h input stage error correction and digital processing clock input stage and duty cycle control system reference and power management adc b core 14-bit pipelined t/h input stage adc1413d dll pll frame assembly serializer a spi output buffer a serializer b output buffer b scrambler a encoder 8-bit/10-bit a scrambler b encoder 8-bit/10-bit b 8-bit 8-bit inap inam clkp clkm inbp scrambler reset inbm 8-bit 8-bit 10-bit 10-bit swing_n swing_n syncp sclk cfg (0 to 3) sdio cs syncn cmlnb cmlpb cmlna cmlpa otr d13 to d0 d13 to d0 otr 005aaa067 refat refab refbb refbt vcma vref sense vcmb
adc1413d_ser all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 6 ? 8 june 2011 4 of 43 nxp semiconductors adc1413d series dual 14-bit adc; serial jesd204a interface 6. pinning information 6.1 pinning 6.2 pin description fig 2. pinning diagram 005aaa068 adc1413d transparent top view dgnd inbm inbp dgnd vcmb vddd refbt cmlpb refbb cmlnb agnd vddd clkm dgnd clkp dgnd agnd vddd refab cmlna refat cmlpa vcma vddd inam dgnd inap dgnd vdda vdda sclk sdio cs agnd reset scrambler cfg0 cfg1 cfg2 cfg3 vddd dgnd vdda vref sense vdda agnd agnd vdda dnc swing_1 swing_0 vddd dgnd syncn syncp 14 29 13 30 12 31 11 32 10 33 9 34 8 35 7 36 6 37 5 38 4 39 3 40 2 41 1 42 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 table 2. pin description symbol pin type [1] description inap 1 i channel a analog input inam 2 i channel a complementary analog input vcma 3 o channel a output common voltage refat 4 o channel a top reference refab 5 o channel a bottom reference agnd 6 g analog ground clkp 7 i clock input clkm 8 i complementary clock input agnd 9 g analog ground refbb 10 o channel b bottom reference refbt 11 o channel b top reference vcmb 12 o channel b output common voltage inbm 13 i channel b complementary analog input
adc1413d_ser all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 6 ? 8 june 2011 5 of 43 nxp semiconductors adc1413d series dual 14-bit adc; serial jesd204a interface inbp 14 i channel b analog input vdda 15 p analog power supply 3 v vdda 16 p analog power supply 3 v sclk 17 i spi clock sdio 18 i/o spi data input/output cs 19 i chip select agnd 20 g analog ground reset 21 i jedec digital ip reset scrambler 22 i scrambler enable and disable cfg0 23 i/o see table 28 (input) or otra (output) [2] cfg1 24 i/o see table 28 (input) or otrb (output) [2] cfg2 25 i/o see table 28 (input) cfg3 26 i/o see table 28 (input) vddd 27 p digital power supply 1.8 v dgnd 28 g digital ground dgnd 29 g digital ground dgnd 30 g digital ground vddd 31 p digital power supply 1.8 v cmlpb 32 o channel b output cmlnb 33 o channel b complementary output vddd 34 p digital power supply 1.8 v dgnd 35 g digital ground dgnd 36 g digital ground vddd 37 p digital power supply 1.8 v cmlna 38 o channel a complementary output cmlpa 39 o channel a output vddd 40 p digital power supply 1.8 v dgnd 41 g digital ground dgnd 42 g digital ground syncp 43 i synchronization from fpga syncn 44 i synchronization from fpga dgnd 45 g digital ground vddd 46 p digital power supply 1.8 v swing_0 47 i jesd204 serial buffer programmable output swing swing_1 48 i jesd204 serial buffer programmable output swing dnc 49 o do not connect vdda 50 p analog power supply 3 v agnd 51 g analog ground agnd 52 g analog ground table 2. pin description ?continued symbol pin type [1] description
adc1413d_ser all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 6 ? 8 june 2011 6 of 43 nxp semiconductors adc1413d series dual 14-bit adc; serial jesd204a interface [1] p: power supply; g: ground; i: input; o: output; i/o: input/output. [2] otra stands for ?out of range a?. otrb stands for ?out of range b? 7. limiting values 8. thermal characteristics [1] value for six layers board in still ai r with a minimum of 25 thermal vias. vdda 53 p analog power supply 3 v sense 54 i reference programming pin vref 55 i/o voltage reference input/output vdda 56 p analog power supply 3 v table 2. pin description ?continued symbol pin type [1] description table 3. limiting values in accordance with the absolute maximum rating system (iec 60134). symbol parameter conditions min max unit v dda analog supply voltage ? 0.4 +4.6 v v ddd digital supply voltage ? 0.4 +2.5 v t stg storage temperature ? 55 +125 ? c t amb ambient temperature ? 40 +85 ? c t j junction temperature - 125 ? c table 4. thermal characteristics symbol parameter conditions typ unit r th(j-a) thermal resistance from junction to ambient [1] 17.8 k/w r th(j-c) thermal resistance from junction to case [1] 6.8 k/w
adc1413d_ser all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 6 ? 8 june 2011 7 of 43 nxp semiconductors adc1413d series dual 14-bit adc; serial jesd204a interface 9. static characteristics table 5. static characteristics [1] symbol parameter conditions min typ max unit supplies v dda analog supply voltage 2.85 3.0 3.4 v v ddd digital supply voltage 1.65 1.8 1.95 v i dda analog supply current f clk = 125 msps; f i =70mhz -343- ma i ddd digital supply current f clk = 125 msps; f i =70mhz -150- ma p tot total power dissipation f clk = 125 msps - 1270 - mw f clk = 105 msps - 1150 - mw f clk =80msps - 995 - mw f clk =65msps - 885 - mw p power dissipation power-down mode - 30 - mw standby mode - 200 - mw clock inputs: pins clkp and clkm (ac-coupled) low-voltage positive em itter-coupled logic (lvpecl) v i(clk)dif differential clock input voltage peak-to-peak - 1.6 - v sine v i(clk)dif differential clock input voltage peak - ? 3.0 - v low voltage complementary metal oxide semiconductor (lvcmos) v il low-level input voltage - - 0.3v dda v v ih high-level input voltage 0.7v dda -- v logic inputs: power-down: pi ns cfg0 to cfg3, scrambler, sw ing_0, swing_1, and reset v il low-level input voltage - 0 - v v ih high-level input voltage - 0.66v ddd -v i il low-level input current ? 6- +6 ? a i ih high-level input current ? 30 - +30 ? a spi: pins cs , sdio, and sclk v il low-level input voltage 0 - 0.3v dda v v ih high-level input voltage 0.7v dda -v dda v i il low-level input current ? 10 - +10 ? a i ih high-level input current ? 50 - +50 ? a c i input capacitance - 4 - pf analog inputs: pins i nap, inam, inbp, and inbm i i input current track mode ? 5- +5 ? a r i input resistance track mode - 15 - ? c i input capacitance track mode - 5 - pf v i(cm) common-mode input voltage track mode 0.9 1.5 2 v
adc1413d_ser all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 6 ? 8 june 2011 8 of 43 nxp semiconductors adc1413d series dual 14-bit adc; serial jesd204a interface b i input bandwidth - 600 - mhz v i(dif) differential input voltage peak-to-peak 1 - 2 v voltage controlled regulator output: pins vcma and vcmb v o(cm) common-mode output voltage -v dda /2 - v i o(cm) common-mode output current -4 - ma reference voltage in put/output: pin vref v vref voltage on pin vref output 0.5 - 1 v input 0.5 - 1 v data outputs: pins cmlpa, cmlna output levels, v ddd = 1.8 v; swing_sel[2:0] = 000 v ol low-level output voltage dc coupled; output - 1.5 - v ac coupled - 1.35 - v v oh high-level output voltage dc coupled; output - 1.8 - v ac coupled - 1.65 - v output levels, v ddd = 1.8 v; swing_sel[2:0] = 001 v ol low-level output voltage dc coupled; output - 1.45 - v ac coupled - 1.275 - v v oh high-level output voltage dc coupled; output - 1.8 - v ac coupled - 1.625 - v output levels, v ddd = 1.8 v; swing_sel[2:0] = 010 v ol low-level output voltage dc coupled; output - 1.4 - v ac coupled - 1.2 - v v oh high-level output voltage dc coupled; output - 1.8 - v ac coupled - 1.6 - v output levels, v ddd = 1.8 v; swing_sel[2:0] = 011 v ol low-level output voltage dc coupled; output - 1.35 - v ac coupled - 1.125 - v v oh high-level output voltage dc coupled; output - 1.8 - v ac coupled - 1.575 - v output levels, v ddd = 1.8 v; swing_sel[2:0] = 100 v ol low-level output voltage dc coupled; output - 1.3 - v ac coupled - 1.05 - v v oh high-level output voltage dc coupled; output - 1.8 - v ac coupled - 1.55 - v serial configuration: pins synccp, synccn v il low-level input voltage differential; input - 0.95 - v v ih high-level input voltage differential; input - 1.47 - v accuracy inl integral non-linearity - ? 5- lsb table 5. static characteristics [1] ?continued symbol parameter conditions min typ max unit
adc1413d_ser all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 6 ? 8 june 2011 9 of 43 nxp semiconductors adc1413d series dual 14-bit adc; serial jesd204a interface [1] typical values measured at v dda =3v, v ddd = 1.8 v, t amb =25 ? c. minimum and maximum values are across the full temperature range t amb = ? 40 ? c to +85 ? c at v dda =3v, v ddd = 1.8 v; v i (inap, inbp) ? v i (inam, inbm) = ? 1 dbfs; internal reference mode; 100 ? differential applied to serial out puts; unless otherwise specified. dnl differential non-linear ity guaranteed no missing codes ? 0.95 ? 0.5 +0.95 lsb e offset offset error - ? 2- mv e g gain error full-scale - ? 0.5 - % m g(ctc) channel-to-channel gain matching -1.1- % supply psrr power supply rejection ratio 200 mv (p-p) on pin vdda; f i =dc - ? 54 - db table 5. static characteristics [1] ?continued symbol parameter conditions min typ max unit
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx adc1413d_ser all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 6 ? 8 june 2011 10 of 43 nxp semiconductors adc1413d series dual 14-bit adc; serial jesd204a interface 10. dynamic characteristics 10.1 dynamic characteristics table 6. dynamic characteristics [1] symbol parameter conditions adc1413d065 adc1413d080 adc1413d105 adc1413d125 unit min typ max min typ max min typ max min typ max analog signal processing ? 2h second harmonic level f i = 3 mhz - 87 - - 87 - - 86 - - 88 - dbc f i =30mhz -86- -86- -86- -87-dbc f i =70mhz -85- -85- -84- -85-dbc f i = 170 mhz - 82 - - 82 - - 81 - - 83 - dbc ? 3h third harmonic level f i = 3 mhz - 86 - - 86 - - 85 - - 87 - dbc f i =30mhz -85- -85- -85- -86-dbc f i =70mhz -84- -84- -83- -84-dbc f i = 170 mhz - 81 - - 81 - - 80 - - 82 - dbc thd total harmonic distortion f i = 3 mhz - 83 - - 83 - - 82 - - 84 - dbc f i =30mhz -82- -82- -82- -83-dbc f i =70mhz -81- -81- -80- -81-dbc f i = 170 mhz - 78 - - 78 - - 77 - - 79 - dbc enob effective number of bits f i =3mhz -11.7--11.7--11.6--11.6-bits f i = 30 mhz - 11.6 - - 11.5 - - 11.5 - - 11.5 - bits f i = 70 mhz - 11.5 - - 11.5 - - 11.4 - - 11.4 - bits f i =170mhz -11.4--11.4--11.3--11.3-bits snr signal-to-noise ratio f i = 3 mhz - 72.1 - - 72.0 - - 71.8 - - 71.4 - dbfs f i = 30 mhz - 71.3 - - 71.2 - - 71.2 - - 71.1 - dbfs f i = 70 mhz - 70.7 - - 70.7 - - 70.6 - - 70.5 - dbfs f i = 170 mhz - 70.2 - - 70.1 - - 70.0 - - 69.9 - dbfs sfdr spurious-free dynamic range f i = 3 mhz - 86 - - 86 - - 85 - - 87 - dbc f i =30mhz -85- -85- -85- -86-dbc f i =70mhz -84- -84- -83- -84-dbc f i = 170 mhz - 81 - - 81 - - 80 - - 82 - dbc
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx adc1413d_ser all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 6 ? 8 june 2011 11 of 43 nxp semiconductors adc1413d series dual 14-bit adc; serial jesd204a interface [1] typical values measured at v dda =3v, v ddd =1.8v, t amb =25 ? c. minimum and maximum values are across the full temperature range t amb = ? 40 ? c to +85 ? c at v dda =3v, v ddd = 1.8 v; v i (inap, inbp) ? v i (inam, inbm) = ? 1 dbfs; internal reference mode; 100 ? differential applied to serial out puts; unless otherwise specified. 10.2 clock and digital output timing [1] typical values measured at v dda =3v, v ddd =1.8v, t amb =25 ? c. minimum and maximum values are across the full temperature range t amb = ? 40 ? c to +85 ? c at v dda =3v, v ddd = 1.8 v; v i (inap, inbp) ? v i (inam, inbm) = ? 1 dbfs; internal reference mode; 100 w differential applied to serial outputs; unless otherwise specified. imd intermodulation distortion f i = 3 mhz - 89 - - 89 - - 88 - - 89 - dbc f i =30mhz -88- -88- -88- -88-dbc f i =70mhz -87- -87- -86- -86-dbc f i = 170 mhz - 84 - - 85 - - 83 - - 84 - dbc ? ct(ch) channel crosstalk f i = 70 mhz - 100 - - 100 - - 100 - - 100 - dbc table 6. dynamic characteristics [1] ?continued symbol parameter conditions adc1413d065 adc1413d080 adc1413d105 adc1413d125 unit min typ max min typ max min typ max min typ max table 7. clock and digital output characteristics [1] symbol parameter conditions adc1413d065 adc1413d080 adc1413d105 adc1413d125 unit min typ max min typ max min typ max min typ max clock timing input: pins clkp and clkm f clk clock frequency 45 - 65 60 - 80 75 - 105 100 - 125 msps t lat(data) data latency time clock cycles 307 - 850 250 - 283 190 - 226 160 - 170 ns ? clk clock duty cycle dcs_en = logic 1 30 50 70 30 50 70 30 50 70 30 50 70 % t d(s) sampling delay time - 0.8 - - 0.8 - - 0.8 - - 0.8 - ns t wake wake-up time -76- -76- -76- -76- ? s
adc1413d_ser all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 6 ? 8 june 2011 12 of 43 nxp semiconductors adc1413d series dual 14-bit adc; serial jesd204a interface 10.3 serial output timing the eye diagram of the serial output is shown in figure 3 and figure 4 . test conditions are: ? 3.125 gbps data rate ? t amb =25c ? dc coupling with two different receiver common-mode voltages fig 3. eye diagram at 1 v receiver common-mode fig 4. eye diagram at 2 v receiver common-mode 005aaa088 005aaa089
adc1413d_ser all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 6 ? 8 june 2011 13 of 43 nxp semiconductors adc1413d series dual 14-bit adc; serial jesd204a interface 10.4 spi timing [1] typical values measured at v dda =3v, v ddd =1.8v, t amb =25 ? c. minimum and maximum values are across the full temperature range t amb = ? 40 ? c to +85 ? c at v dda =3v, v ddd = 1.8 v; v i (inap, inbp) ? v i (inam,inbm) = ? 1 dbfs; internal reference mode; 100 ? differential applied to serial outputs; unless otherwise specified. table 8. spi timing characteristics [1] symbol parameter conditions min typ max unit t w(sclk) sclk pulse width - 40 - ns t w(sclkh) sclk high pulse width -16- ns t w(sclkl) sclk low pulse width -16- ns t su set-up time data to sclkh - 5 - ns cs to sclkh - 5 - ns t h hold time data to sclkh - 2 - ns cs to sclkh - 2 - ns f clk(max) maximum clock frequency -25- mhz fig 5. spi timing t su sdio sclk r/w w1 w0 a12 a11 d2 d1 d0 t su t h t h t w(sclk) 005aaa065 cs t w(sclkl) t w(sclkh)
adc1413d_ser all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 6 ? 8 june 2011 14 of 43 nxp semiconductors adc1413d series dual 14-bit adc; serial jesd204a interface 11. application information 11.1 analog inputs 11.1.1 input stage description the analog input of the adc1413d supports a di fferential or a single-ended input drive. optimal performance is achieved using diff erential inputs with the common-mode input voltage (v i(cm) ) on pins inxp and inxm set to 0.5v dda . the full-scale analog input voltage range is configurable between 1 v (p-p) and 2 v (p-p) via a programmable internal reference (see section 11.2 and table 21 ). figure 6 shows the equivalent circuit of the sample-and-hold input stage, including electrostatic discharge (esd) protection and circuit and package parasitics. the sample phase occurs when the internal clock (derived from the clock signal on pin clkp/clkm) is high. the voltage is then he ld on the sampling capacitors. when the clock signal goes low, the stage enters the hold phase and the voltage information is transmitted to the adc core. fig 6. input sampling circuit 005aaa069 inap inbp package esd parasitics switch r on = 15 4 pf 4 pf c s c s switch r on = 15 inam inbm 1, 14 2, 13 internal clock internal clock
adc1413d_ser all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 6 ? 8 june 2011 15 of 43 nxp semiconductors adc1413d series dual 14-bit adc; serial jesd204a interface 11.1.2 anti-kickback circuitry anti-kickback circuitry (rc filter in figure 7 ) is needed to counteract the effects of a charge injection generated by the sampling capacitance. the rc filter is also used to filter noise from the signal before it reaches the sampling stage. the value of the capacitor should be ch osen to maximize noise attenuation without degrading the settling time excessively. the component values are determined by the input frequency and should be selected so as not to affect the input bandwidth. 11.1.3 transformer the configuration of the transf ormer circuit is determined by the input frequency. the configuration shown in figure 8 would be suitable for a baseband application. fig 7. anti-kickback circuit table 9. rc coupling versus input frequency, typical values input frequency (mhz) resistance ( ? ) capacitance (pf) 32512 70 12 8 170 12 8 001aan679 r r c inap/ inbp inam/ inbm fig 8. single transformer configuration 005aaa070 100 nf 100 nf 100 nf 100 nf 100 nf 25 25 25 25 12 pf adt1-1wt 100 nf analog input inap inbp inam inbm vcm
adc1413d_ser all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 6 ? 8 june 2011 16 of 43 nxp semiconductors adc1413d series dual 14-bit adc; serial jesd204a interface the configuration shown in figure 9 is recommended for high frequency applications. in both cases, the choice of transformer is a compromise between cost and performance. 11.2 system reference and power management 11.2.1 internal/external reference the adc1413d has a stable and accurate built-in internal reference voltage to adjust the adc full-scale. this reference voltage can be se t internally via spi or with pins vref and sense (see figure 11 to figure 14 ), in 1 db steps between 0 db and ? 6 db, via spi control bits intref[2:0] (when bit intref_en = logic 1; see ta b l e 2 1 ). the equivalent reference circuit is shown in figure 10 . an external reference is also possible by providing a voltage on pin vref as described in figure 13 . fig 9. dual transformer configuration 005aaa071 100 nf 100 nf 100 nf 100 nf 12 12 8.2 pf 50 50 50 50 adt1-1wt adt1-1wt analog input inap inbp inam vcm inbm
adc1413d_ser all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 6 ? 8 june 2011 17 of 43 nxp semiconductors adc1413d series dual 14-bit adc; serial jesd204a interface if bit intref_en is set to logic 0, the referenc e voltage is determined either internally or externally as detailed in ta b l e 1 0 . figure 11 to figure 14 illustrate how to connect the sen se and vref pins to select the required reference voltage source. fig 10. reference equivalent schematic table 10. reference modes mode spi bit, ?internal reference? sense pin vref pin full-scale (v (p-p)) internal ( figure 11 ) 0 gnd 330 pf capacitor to gnd 2 internal ( figure 12 ) 0 vref pin = sense pin and 330 pf capacitor to gnd 1 external ( figure 13 )0 v dda external voltage from 0.5 v to 1 v 1 to 2 internal, spi mode ( figure 14 ) 1 vref pin = sense pin and 330 pf capacitor to gnd 1 to 2 ext_ref ext_ref 001aan670 refat/ refbt refab/ refbb sense vref selection logic bandgap reference adc core buffer reference amp
adc1413d_ser all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 6 ? 8 june 2011 18 of 43 nxp semiconductors adc1413d series dual 14-bit adc; serial jesd204a interface 11.2.2 programmable full-scale the full-scale is programmable between 1 v (p-p) to 2 v (p-p) (see ta b l e 11 ). fig 11. internal reference, 2 v (p-p) full-scale fig 12. internal reference, 1 v (p-p) full-scale fig 13. external reference, 1 v (p-p) to 2 v (p-p) full-scale fig 14. internal reference vi a spi, 1 v (p-p) to 2 v (p-p) full-scale 330 pf vref sense 005aaa116 reference equivalent schematic 330 pf 005aaa117 vref sense reference equivalent schematic 0.1 f vdda v 005aaa119 vref sense reference equivalent schematic reference equivalent schematic 330 pf 005aaa118 vref sense table 11. programmable full-scale intref[2:0] level (db) full-scale (v (p-p)) 000 0 2 001 ? 11.78 010 ? 21.59 011 ? 31.42 100 ? 41.26 101 ? 51.12 110 ? 61 111 not used x
adc1413d_ser all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 6 ? 8 june 2011 19 of 43 nxp semiconductors adc1413d series dual 14-bit adc; serial jesd204a interface 11.2.3 common-mode output voltage (v o(cm) ) an 0.1 ? f filter capacitor should be connecte d between pins vcma and vcmb and ground to ensure a low-noise common-mode output voltage. when ac-coupled, these pins can be used to set the common-mode reference for the analog inputs, for instance via a transformer middle point. 11.2.4 biasing the common-mode input voltage, v i(cm) , at the inputs to the sample-and-hold stage (pins inam, inbm, inap, and inbp) must be between 0.9 v and 2 v for optimal performance. 11.3 clock input 11.3.1 drive modes the adc1413d can be driven differentially (lvpecl). it can also be driven by a single-ended low voltage complementary metal oxide semiconductor (lvcmos) signal connected to pin clkp (pin clkm should be connected to ground via a capacitor) or pin clkm (pin clkp should be connected to ground via a capacitor). fig 15. reference equivalent schematic 1.5 v vcma vcmb 0.1 f package esd parasitics 005aaa077 common mode reference adc core a. rising edge lvcmos b. falling edge lvcmos fig 16. lvcmos single-ended clock input lvcmos clock input clkp clkm 005aaa174 005aaa053 lvcmos clock input clkp clkm
adc1413d_ser all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 6 ? 8 june 2011 20 of 43 nxp semiconductors adc1413d series dual 14-bit adc; serial jesd204a interface 11.3.2 equivalent input circuit the equivalent circuit of the input clock buffer is shown in figure 18 . the common-mode voltage of the differential input stage is set via 5 k ? internal resistors. a. sine clock input b. sine clock input (with transformer) c. lvpecl clock input fig 17. differential clock input sine clock input clkp clkm 005aaa173 sine clock input clkp clkm 005aaa054 lvpecl clock input 005aaa172 clkp clkm v cm(clk) = common-mode voltage of the differential input stage. fig 18. equivalent input circuit clkp clkm 005aaa081 5 k 5 k v cm(clk) se_sel se_sel package esd parasitics
adc1413d_ser all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 6 ? 8 june 2011 21 of 43 nxp semiconductors adc1413d series dual 14-bit adc; serial jesd204a interface single-ended or differential clock inputs can be selected via the spi (see ta b l e 2 0 ). if single-ended is selected, the input pin (clkm or clkp) is selected via control bit se_sel. if single-ended is implemented without settin g bit se_sel accordingly, the unused pin should be connected to ground via a capacitor. 11.3.3 duty cycle stabilizer the duty cycle stabilizer can improve th e overall performance of the adc by compensating the input clock signal duty cycle . when the duty cycle stabilizer is active (bit dcs_en = logic 1; see table 20 ), the circuit can handle signals with duty cycles of between 30 % and 70 % (typical). when t he duty cycle stabilizer is disabled (dcs_en = logic 0), the input clock signal s hould have a duty cycle of between 45 % and 55 %. 11.3.4 clock input divider the adc1413d contains an input clock divider that divides the incoming clock by a factor of 2 (when bit clkdiv2_sel = logic 1; see ta b l e 2 0 ). this feature allows the user to deliver a higher clock frequency with better jitter performance, leading to a better snr result once acquisition has been performed. 11.4 digital outputs 11.4.1 serial output equivalent circuit the jesd204a standard specifies that if the receiver and the transmitter are dc-coupled, both must be fed fr om the same supply. the output should be terminated when 100 ? (typical) is reached at the receiver side. table 12. duty cycle stabilizer bit dcs_en description 0 duty cycle stabilizer disable 1 duty cycle stabilizer enable fig 19. cml output connection to the receiver (dc-coupled) vddd cmlpa/clmpb cmlna/clmnb agnd 005aaa082 12 ma to 26 ma 100 + receiver 50 ?
adc1413d_ser all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 6 ? 8 june 2011 22 of 43 nxp semiconductors adc1413d series dual 14-bit adc; serial jesd204a interface 11.5 jesd204a serializer for more information about the jesd204a standard refer to the jedec web site. 11.5.1 digital jesd204a formatter the block placed after the adc cores is used to implement all functionalities of the jesd204a standard. this ensures signal inte grity and guarantees the clock and the data recovery at the receiver side. the block is highly parameterized and can be configured in various ways depending on the sampling frequency and the number of lanes used. fig 20. cml output connection to the receiver (ac-coupled) cmlpa/cmlpb cmlna/cmlnb 12 ma to 26 ma 100 50 10 nf 10 nf 005aaa083 vddd ? + receiver fig 21. general overview of the jesd204a serializer frame to octets f octets scrambler tx transport layer cf: position of control bits hd: frame boundary break padding with tail bits (tt) mx(n'xs) bits lx(f) octets l octets n' = n+cs s samples per frame cycle samples stream to lane stream mapping n bits from cr 0 + cs bits for control n bits from cr m ? 1 + cs bits for control m converters l lanes lane 1 frame to octets f octets scrambler 8-bit/ 10-bit ser tx controller lane 0 8-bit/ 10-bit ser alignment character generator alignment character generator sync~ 005aaa084
adc1413d_ser all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 6 ? 8 june 2011 23 of 43 nxp semiconductors adc1413d series dual 14-bit adc; serial jesd204a interface 11.5.2 adc core output codes versus input voltage ta b l e 1 3 shows the data output codes for a given analog input voltage. fig 22. detailed view of the jesd204a serializer with debug functionality n and cs n and cs 00 scr scr prbs 8-bit/ 10-bit 01 00 01 00 01 10 11 8-bit/ 10-bit prbs '0' '0/1' prbs '0' '0/1' prbs 8 8 n + cs n + cs 14 + 1 14 + 1 14 + 1 adc a pll and dll frame clk character clk bit clk 10 10 11 10 01 00 ser ser 11 10 00 11 10 00 1 f 10f dummy adc_pd adc_pd adc b prbs fsm (frame assembly, character replication; ila, test mode) frame assembly 005aaa085 sync_request 14 + 1 adc_mode[1:0] scr_in_mode scr_in_mode lane_mode[1:0] swing_sel[2:0] lane_pol lane_mode[1:0] lane_pol 14 + 1 14 + 1 dummy prbs adc_mode[1:0] table 13. output codes versus input voltage inp ? inm (v) offset binary two?s complement otr < ? 1 00 0000 0000 0000 1 0 0000 0000 0000 1 ? 1 00 0000 0000 0000 1 0 0000 0000 0000 0 ? 0.9998779 00 0000 0000 0001 1 0 0000 0000 0001 0 ? 0.9997559 00 0000 0000 0010 1 0 0000 0000 0010 0 ? 0.9996338 00 0000 0000 0011 1 0 0000 0000 0011 0 ? 0.9995117 00 0000 0000 0100 1 0 0000 0000 0100 0 .... .... .... 0 ? 0.0002441 01 1111 1111 1110 1 1 1111 1111 1110 0 ? 0.0001221 01 1111 1111 1111 1 1 1111 1111 1111 0 0 10 0000 0000 0000 0 0 0000 0000 0000 0 + 0.000122 1 10 0000 0000 0001 0 0 0000 0000 0001 0 + 0.0002441 10 0000 0000 0010 0 0 0000 0000 0010 0 .... .... .... 0 + 0.9995117 11 1111 1111 1 011 0 1 1111 1111 1 011 0
adc1413d_ser all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 6 ? 8 june 2011 24 of 43 nxp semiconductors adc1413d series dual 14-bit adc; serial jesd204a interface 11.6 serial peripheral interface (spi) 11.6.1 register description the adc1413d serial interface is a synchr onous serial communications port allowing easy interfacing with many industry microprocessors. it provides access to the registers that control the operation of the chip in both read and write modes. this interface is configured as a 3- wire type (sdio as bidirectional pin). sclk acts as the serial clock, and pin cs acts as the serial chip select. each read/write operation is sequenced by the cs signal and enabled by a low level to to drive the chip with 2 bytes to 5 bytes, depe nding on the content of the instruction byte (see table 14 ). [1] r/w indicates whether a read (logic 1) or write (l ogic 0) transfer occurs after the instruction byte. [1] bits w1 and w0 indicate the number of bytes transferred after the instruction byte. bits a12 to a0 indicate the address of the register being accessed. in the case of a multiple byte transfer, this address is the first register to be accessed. an address counter is incremented to access subsequent addresses. + 0.9996338 11 1111 1111 110 00 1 1111 1111 110 0 0 + 0.9997559 11 1111 1111 11 01 0 1 1111 1111 11 01 0 + 0.9998779 11 1111 1111 1110 0 1 1111 1111 1110 0 + 1 11 1111 1111 1111 0 1 1111 1111 1111 0 > + 1 11 1111 1111 1111 0 1 1111 1111 1111 1 table 13. output codes versus input voltage ?continued inp ? inm (v) offset binary two?s complement otr table 14. spi instruction bytes msb lsb bit 76543210 description r/w [1] w1 w0 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 table 15. read or write mode access description r/w [1] description 0 write mode operation 1 read mode operation table 16. number of bytes to be transferred w1 w0 number of bytes transferred 001 byte 012 bytes 103 bytes 1 1 4 or more bytes
adc1413d_ser all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 6 ? 8 june 2011 25 of 43 nxp semiconductors adc1413d series dual 14-bit adc; serial jesd204a interface the steps for a data transfer: 1. the falling edge on pin cs in combination with a rising edge on pin sclk determine the start of communications. 2. the first phase is the transfer of the 2-byte instruction. 3. the second phase is the transfer of the data which can vary in length but is always a multiple of 8 bits. the most significant bit (msb) is always sent first (for instruction and data bytes). 4. a rising edge on pin cs indicates the end of data transmission. 11.6.2 channel control the two adc channels can be configured at the same time or separately. by using the register ?channel index?, the user can ch oose which adc channel receives the next spi-instruction. by default the channel a and b receives the same instructions in write mode. in read mode only a is active. fig 23. transfer diagram for tw o data bytes (3-wire type) cs sclk sdio r/w w1 w0 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d3 d2 d1 d0 d0 d7 d6 d5 d4 instruction bytes register n (data) register n + 1 (data) 005aaa086
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx adc1413d_ser all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 6 ? 8 june 2011 26 of 43 nxp semiconductors adc1413d series dual 14-bit adc; serial jesd204a interface table 17. register allocation map address (hex) register name access [1] bit definition default (bin) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 adc control register 0003 channel index r/w - - - - - - adcb adca 1111 1111 0005 reset and power-down modes r/w sw_rst - - - - - pd[1:0] 0000 0000 0006 clock r/w - - - se_sel diff_se - clkdiv2_sel dcs_en 0000 0001 0008 vref r/w - - - - intref_en intref[2:0] 0000 0000 0013 offset r/w - - dig_offset[5:0] 0000 0000 0014 test pattern 1 r/w - - - - - testpat_1[2:0] 0000 0000 0015 test pattern 2 r/w testpat_2[13:6] 0000 0000 0016 test pattern 3 r/w testpat_3[5:0] - - 0000 0000 jesd204a control 0801 ser_status r rxsync_ error reserved[2:0] 0 0 por_tst reserved 0100 0000 0802 ser_reset r/w sw_rst 0 0 0 fsm_sw_ rst 0 0 0 0000 0000 0803 ser_cfg_setup r/w 0 0 0 0 cfg_setup[3:0] 0000 1000 0805 ser_control1 r/w 0 tristate_ cfg_pins sync_ pol sync_ single_ ended 1 rev_ scr rev_ encoder rev_serial 0100 1001 0806 ser_control2 r/w 0 0 0 0 0 0 swap_ lane_1_2 swap_ adc_0_1 0000 0011 0808 ser_analog_ctrl r/w 0 0 0 0 0 swing_sel[2:0] 0000 0011 0809 ser_scramblera r/w 0 lsb_init[6:0] 0000 0000 080a ser_scramblerb r/w msb_init[7:0] 1111 1111 080b ser_prbs_ctrl r/w 0 0 0 0 0 0 prbs_type[1:0] 0000 0000 0820 cfg_0_did r* did[7:0] 1110 1101 0821 cfg_1_bid r/w* 0 0 0 0 bid[3:0] 0000 1010 0822 cfg_3_scr_l r/w* scr 0 0 0 0 0 0 l 0000 0000 0823 cfg_4_f r/w* 0 0 0 0 0 f[2:0] 0000 0001 0824 cfg_5_k r/w* 0 0 0 k[4:0] 0000 1000 0825 cfg_6_m r/w* 0 0 0 0 0 0 0 m 0000 0000
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx adc1413d_ser all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 6 ? 8 june 2011 27 of 43 nxp semiconductors adc1413d series dual 14-bit adc; serial jesd204a interface [1] an "*" in the access column means that this register is subject to control acce ss conditions in write mode. 0826 cfg_7_cs_n r/w* 0 cs[0] 0 0 n[3:0] 0100 0100 0827 cfg_8_np r/w 0 0 0 np[4:0] 0000 1111 0828 cfg_9_s r/w* 0 0 0 0 0 0 0 s 0000 0000 0829 cfg_10_hd_cf r/w* hd 0 0 0 0 0 cf[1:0] 0000 0000 082c cfg_01_2_lid r/w* 0 0 0 lid[4:0] 0001 1011 082d cfg_02_2_lid r/w* 0 0 0 lid[4:0] 0001 1100 084c cfg01_13_fchk r fchk[7:0] 0000 0000 084d cfg02_13_fchk r fchk[7:0] 0000 0000 0870 lane0_0_ctrl r/w 0 scr_in_ mode lane_mode[1:0] 0 lane_ pol lane_clk_ pos_edge lane_pd 0000 0001 0871 lane1_0_ctrl r/w 0 scr_in_ mode lane_mode[1:0] 0 lane_ pol lane_clk_ pos_edge lane_pd 0000 0000 0890 adca_0_ctrl r/w 0 0 adc_mode[1:0] 0 0 0 adc_pd 0000 0001 0891 adcb_0_ctrl r/w 0 0 adc_mode[1:0] 0 0 0 adc_pd 0000 0000 table 17. register allocation map ?continued address (hex) register name access [1] bit definition default (bin) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
adc1413d_ser all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 6 ? 8 june 2011 28 of 43 nxp semiconductors adc1413d series dual 14-bit adc; serial jesd204a interface 11.6.3 register description 11.6.3.1 adc control registers table 18. register channel index (address 0003h) default values are highlighted. bit symbol access value description 7 to 2 - - 111111 not used 1 adcb r/w adc b gets the next spi command: 0 adc b not selected 1 adc b selected 0 adca r/w adc a gets the next spi command: 0adc a not selected 1 adc a selected table 19. register reset and power-down mode (address 0005h) default values are highlighted. bit symbol access value description 7 sw_rst r/w reset digital part: 0 no reset 1 performs a reset of the digital part 6 to 2 - - 00000 not used 1 to 0 pd[1:0] r/w power-down mode: 00 normal (power-up) 01 full power-down 10 sleep 11 normal (power-up) table 20. register clock (address 0006h) default values are highlighted. bit symbol access value description 7 to 5 - - 000 not used 4 se_sel r/w select se clock input pin: 0 select clkm input 1 select clkp input 3 diff_se r/w differential/single-ended clock input select: 0 fully differential 1 single-ended 2 - - 0 not used 1 clkdiv2_sel r/w select clock input divider by 2: 0 disable 1 active 0 dcs_en r/w duty cycle stabilizer enable: 0 disable 1 active
adc1413d_ser all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 6 ? 8 june 2011 29 of 43 nxp semiconductors adc1413d series dual 14-bit adc; serial jesd204a interface table 21. register vref (address 0008h) default values are highlighted. bit symbol access value description 7 to 4 - - 0000 not used 3 intref_en r/w enable internal programmable vref mode: 0 disable 1 active 2 to 0 intref[2:0] r/w programmable internal reference: 000 0 db (fs=2 v) 001 ? 1 db (fs=1.78 v) 010 ? 2 db (fs=1.59 v) 011 ? 3 db (fs=1.42 v) 100 ? 4 db (fs=1.26 v) 101 ? 5 db (fs=1.12 v) 110 ? 6 db (fs=1 v) 111 not used table 22. digital offset adjustment (address 0013h) default values are highlighted. register offset decimal dig_offset[5:0] +31 011111 +31 lsb ... ... ... 0 000000 0 ... ... ... ? 32 100000 ? 32 lsb table 23. register test pattern 1 (address 0014h) default values are highlighted. bit symbol access value description 7 to 3 - - 00000 not used 2 to 0 testpat_1[2:0] r/w digital test pattern: 000 off 001 mid-scale 010 ? fs 011 + fs 100 toggle ?1111..1111?/?0000..0000? 101 custom test pattern, to be written in register 0015h and 0016h 110 ?010101...? 111 ?101010...?
adc1413d_ser all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 6 ? 8 june 2011 30 of 43 nxp semiconductors adc1413d series dual 14-bit adc; serial jesd204a interface 11.6.4 jesd204a digital control registers table 24. register test pattern 2 (address 0015h) default values are highlighted. bit symbol access value description 7 to 0 testpat_2[13:6] r/w 00000000 custom digital test pattern (bit 13 to 6) table 25. register test pattern 3 (address 0016h) default values are highlighted. bit symbol access value description 7 to 2 testpat_3[5:0] r/w 000000 custom digital test pattern (bit 5 to 0) 1 to 0 - - 00 not used table 26. ser_status (address 0801h) default values are highlighted. bit symbol access value description 7 rxsync_error r 0 set to 1 when a synchronization error occurs 6 to 4 reserved[2:0] - 100 reserved 3 to 2 - - 00 not used 1por_tst r 0 power-on-reset 0 reserved - 0 reserved table 27. ser_reset (address 0802h) default values are highlighted. bit symbol access value description 7sw_rst r/w 0 initiates a software reset of the jesd204a unit 6 to 4 - - 000 not used 3fsm_sw_rstr/w 0 initiates a software reset of the internal state machine of jesd204a unit 2 to 0 - - 000 not used
adc1413d_ser all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 6 ? 8 june 2011 31 of 43 nxp semiconductors adc1413d series dual 14-bit adc; serial jesd204a interface [1] f: octets per frame clock cycle hd: high-density mode k: frame per multi-frame m: converters per device l: lane per converter device cs: number of control bits per conversion sample cf: control words per frame clock cycle and link s: number of samples transmitted per single converter per frame cycle table 28. ser_cfg_setup (address 0803h) default values are highlighted. bit symbol access value description 7 to 4 - - 0000 not used 3 to 0 cfg_setup[3:0] r/w quick configuration of jesd204a. these settings overrule the configuration of pins cfg3 to cfg0 (see table 29 ). table 29. jesd204a configuration table cfg_setup[3:0] adc a adc b lane 0 lane 1 f [1] hd [1] k [1] m [1] l [1] comment cs [1] cf [1] s [1] 0 0000 on on on on 20922(f ? k) ? 17 1 0 1 1 0001 on on on off 4 0 5 2 1 (f ? k) ? 17 1 0 1 2 0010 on on off on 40521(f ? k) ? 17 1 0 1 3 0011 on off on on 111712(f ? k) ? 17 1 0 1 4 0100 off on on on 111712(f ? k) ? 17 1 0 1 5 0101 on off on off 2 0 9 1 1 (f ? k) ? 17 1 0 1 60110 on off off on 20911(f ? k) ? 17 1 0 1 70111 off on on off 2 0 9 1 1 (f ? k) ? 17 1 0 1 8 1000 off on off on 20911(f ? k) ? 17 1 0 1 9 1001 reserved 10 1010 reserved 11 1011 reserved 12 1100 reserved 13 1101 reserved 14 1110 on on on on 2 0 9 2 2 test: loop alignment 101 15 1111 off off off off 2 0 9 2 2 chip power-down 101
adc1413d_ser all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 6 ? 8 june 2011 32 of 43 nxp semiconductors adc1413d series dual 14-bit adc; serial jesd204a interface table 30. ser_control1 (address 0805h) default values are highlighted. bit symbol access value description 7 - - 0 not used 6 tristate_cfg_pins r/w 1 pins cfg3 to cfg0 are set to high-impedance. switch to 0 automatically after start-up or reset. 5 sync_pol r/w defines the sync signal polarity: 0 synchronization signal is active low 1 synchronization signal is active high 4 sync_single_ended r/w defines the input mode of the sync signal: 0 synchronization input mode is set in differential mode 1 synchronization input mode is set in single-ended mode 3 - - 1 not used 2 rev_scr - lsbs are swapped with msbs at the scrambler input: 0 disable 1 enable 1 rev_encoder - lsbs are swapped with m sbs at the 8-bit/10-bit encoder input: 0 disable 1 enable 0 rev_serial - lsbs are swapped with msbs at the lane input: 0 disable 1enable table 31. ser_control2 (address 0806h) default values are highlighted. bit symbol access value description 7 to 2 - - 000000 not used 1 swap_lane_0_1 r/w swaps the outputs of the jesd204a unit. (output buffer a is connected to lane 1, output buffer b is connected to lane 0): 0 disable 1enable 0 swap_adc_a_b r/w swaps the inputs of the jesd204a unit. (adc a output is connected to input b, adc b is connected to input a): 0 disable 1enable table 32. ser_analog_ctrl (address 0808h) default values are highlighted. bit symbol access value description 7 to 3 - - 00000 not used 2 to 0 swing_sel[2:0] r/w 011 defines the swing output for the lane pads
adc1413d_ser all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 6 ? 8 june 2011 33 of 43 nxp semiconductors adc1413d series dual 14-bit adc; serial jesd204a interface table 33. ser_scramblera (address 0809h) default values are highlighted. bit symbol access value description 7 - - 0 not used 6 to 0 lsb_init[6:0] r/w 0000000 defines the initialization vector for the scrambler polynomial (lower) table 34. ser_scramblerb (address 080ah) default values are highlighted. bit symbol access value description 7 to 0 msb_init[7:0] r/w 11111111 defines the initialization vector for the scrambler polynomial (upper) table 35. ser_prbs_ctrl (address 080bh) default values are highlighted. bit symbol access value description 7 to 2 - - 000000 not used 1 to 0 prbs_type[1:0] r/w defines the type of pseudo-random binary sequence (prbs) generator to be used: 00 (reset) prbs-7 01 prbs-7 10 prbs-23 11 prbs-31 table 36. cfg_0_did (address 0820h) default values are highlighted. bit symbol access value description 7 to 0 did[7:0] r 11101101 defines the device (= link) identification number table 37. cfg_1_bid (address 0821h) default values are highlighted. bit symbol access value description 7 to 4 - - 0000 not used 3 to 0 bid[3:0] r/w 1010 defines the bank id ? extension to did table 38. cfg_3_scr_l (address 0822h) default values are highlighted. bit symbol access value description 7 scr r/w 0 scrambling enabled 6 to 1 - - 000000 not used 0 l r/w 0 defines the number of lanes per converter device, minus 1 table 39. cfg_4_f (address 0823h) default values are highlighted. bit symbol access value description 7 to 3 - - 00000 not used 2 to 0 f[2:0] r/w 001 defines the number of octets per frame, minus 1
adc1413d_ser all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 6 ? 8 june 2011 34 of 43 nxp semiconductors adc1413d series dual 14-bit adc; serial jesd204a interface table 40. cfg_5_k (address 0824h) default values are highlighted. bit symbol access value description 7 to 5 - - 000 not used 4 to 0 k[4:0] r/w 01000 defines the number of frames per multiframe, minus 1 table 41. cfg_6_m (address 0825h) default values are highlighted. bit symbol access value description 7 to 1 - - 0000000 not used 0 m r/w 0 defines the number of converters per device, minus 1 table 42. cfg_7_cs_n (address 0826h) default values are highlighted. bit symbol access value description 7 - - 0 not used 6 cs[0] r/w 1 defines the number of control bits per sample, minus 1 5 to 4 - r 00 not used 3 to 0 n[3:0] r/w 0100 defines the converter resolution table 43. cfg_8_np (address 0827h) default values are highlighted. bit symbol access value description 7 to 5 - - 000 not used 4 to 0 np[4:0] r/w 01111 defines the total number of bits per sample, minus 1 table 44. cfg_9_s (address 0828h) default values are highlighted. bit symbol access value description 7 to 1 - - 0000000 not used 0s r/w 0 defines number of samples per converter per frame cycle table 45. cfg_10_hd_cf (address 0829h) default values are highlighted. bit symbol access value description 7 hd r/w 0 defines high density format 6 to 2 - - 00000 not used 1 to 0 cf[1:0] r/w 00 defines number of cont rol words per frame clock cycle per link. table 46. cfg_01_2_lid (address 082ch) default values are highlighted. bit symbol access value description 7 to 5 - - 000 not used 4 to 0 lid[4:0] r/w 11011 defines lane 0 identification number
adc1413d_ser all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 6 ? 8 june 2011 35 of 43 nxp semiconductors adc1413d series dual 14-bit adc; serial jesd204a interface table 47. cfg_02_2_lid (address 082dh) default values are highlighted. bit symbol access value description 7 to 5 - - 000 not used 4 to 0 lid[4:0] r/w 11100 defines lane 1 identification number table 48. cfg01_13_fchk (address 084ch) default values are highlighted. bit symbol access value description 7 to 0 fchk[7:0] r 00000000 defines the checksum value for lane 0 checksum corresponds to the sum of all the link configuration parameters modulo 256 (as defined in jedec standard no.204a) table 49. cfg02_13_fchk (address 084dh) default values are highlighted. bit symbol access value description 7 to 0 fchk[7:0] r 00000000 defines the checksum value for lane 1 checksum corresponds to the sum of all the link configuration parameters module 256 (as defined in jedec standard no.204a) table 50. lane0_0_ctrl (address 0870h) default values are highlighted. bit symbol access value description 7 - - 0 not used 6 scr_in_mode r/w defines the input type fo r scrambler and 8-bit/10-bit units: 0 (reset) (normal mode) = input of the scrambler and 8-bit/10-bit units is the output of the frame assembly unit. 1 input of the scrambler and 8- bit/10-bit units is the prbs generator (prbs type is defined with ?prbs_type[1:0]? (ser_prbs_ctrl register) 5 to 4 lane_mode[1:0] r/w defines output type of lane output unit: 00 (reset) normal mode: lane output is the 8-bit/10-bit output unit 01 constant mode: lane output is set to a constant (0 ? 0) 10 toggle mode: lane output is toggling between 0 ? 0 and 0 ? 1 11 prbs mode: lane output is th e prbs generator (prbs type is defined with ?prbs_type[1:0] ? (ser_prbs_ctrl register) 3 - - 0 not used 2 lane_pol r/w defines lane polarity: 0 lane polarity is normal 1 lane polarity is inverted 1 lane_clk_pos_edge r/w defi nes lane clock polarity: 0 lane clock provided to the serializer is active on positive edge 1 lane clock provided to the serializer is active on negative edge
adc1413d_ser all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 6 ? 8 june 2011 36 of 43 nxp semiconductors adc1413d series dual 14-bit adc; serial jesd204a interface 0 lane_pd r/w lane power-down control: 0 lane is operational 1 lane is in power-down mode table 50. lane0_0_ctrl (address 0870h) ?continued default values are highlighted. bit symbol access value description table 51. lane1_0_ctrl (address 0871h) default values are highlighted. bit symbol access value description 7 - - 0 not used 6 scr_in_mode r/w defines the input type for scrambler and 8-bit/10-bit units: 0 (reset) (normal mode) = input of the scrambler and 8-bit/10-bit units is the output of the frame assembly unit. 1 input of the scrambler and 8-bit/10-bit units is the prbs generator (prbs type is defined with ?prbs_type[1:0]? (ser_prbs_ctrl register) 5 to 4 lane_mode[1:0] r/w defines output type of lane output unit: 00 (reset) normal mode: lane output is the 8-bit/10-bit output unit 01 constant mode: lane output is set to a constant (0x0) 10 toggle mode: lane output is toggling between 0x0 and 0x1 11 prbs mode: lane output is th e prsb generator (prbs type is defined with ?prbs_type[1:0] ? (ser_prbs_ctrl register) 3 - - 0 not used 2 lane_pol r/w defines lane polarity: 0 lane polarity is normal 1 lane polarity is inverted 1 lane_clk_pos_edge r/w defi nes lane clock polarity: 0 lane clock provided to the serializer is active on positive edge 1 lane clock provided to the serializer is active on negative edge 0 lane_pd r/w lane power-down control: 0 lane is operational 1 lane is in power-down mode
adc1413d_ser all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 6 ? 8 june 2011 37 of 43 nxp semiconductors adc1413d series dual 14-bit adc; serial jesd204a interface table 52. adca_0_ctrl (address 0890h) default values are highlighted. bit symbol access value description 7 to 6 - - 00 not used 5 to 4 adc_mode[1:0] r/w defines input type of jesd204a unit: 00 (reset) adc output is connected to the jesd204a input 01 not used 10 jesd204a input is fed with a dummy constant, set to: otr = 0 and adc[13:0] = ?10011011101010? 11 jesd204a is fed with a prbs generator (prbs type is defined with ?prbs_type[1:0]? (s er_prbs_ctrl register) 3 to 1 - - 000 not used 0 adc_pd r/w adc power-down control: 0 adc is operational 1 adc is in power-down mode table 53. adcb_0_ctrl (address 0891h) default values are highlighted. bit symbol access value description 7 to 6 - - 00 not used 5 to 4 adc_mode[1:0] r/w defines input type of jesd204a unit 00 (reset) adc output is connected to the jesd204a input 01 not used 10 jesd204a input is fed with a dummy constant, set to: otr = 0 and adc[13:0] = ?10011011101010? 11 jesd204a is fed with a prbs generator (prbs type is defined with ?prbs_type[1:0]? (s er_prbs_ctrl register) 3 to 1 - - 000 not used 0 adc_pd r/w adc power-down control: 0 adc is operational 1 adc is in power-down mode
adc1413d_ser all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 6 ? 8 june 2011 38 of 43 nxp semiconductors adc1413d series dual 14-bit adc; serial jesd204a interface 12. package outline fig 24. package outline sot684-7 (hvqfn56) references outline version european projection issue date iec jedec jeita sot684-7 - - - mo-220 - - - sot684-7_po 08-11-19 09-03-04 unit mm max nom min 1.00 0.85 0.80 0.05 0.02 0.00 0.2 8.1 8.0 7.9 5.95 5.80 5.65 8.1 8.0 7.9 0.5 6.5 0.5 0.4 0.3 0.1 a (1) dimensions note 1. plastic or metal protrusions of 0.075 mm maximum per side are not included. hvqfn56: plastic thermal enhanced very thin quad flat package; no leads; 56 terminals; body 8 x 8 x 0.85 mm sot684-7 a 1 b 0.30 0.21 0.18 cd (1) d h e (1) e h 6.55 6.40 6.25 ee 1 e 2 6.5 lv 0.1 w 0.05 y 0.05 y 1 0 2.5 5 mm scale terminal 1 index area b a d e c y c y 1 x detail x a c a 1 b e 2 e 1 e e 1/2 e 1/2 e a c b v c w terminal 1 index area d h e h 1 15 14 29 42 28 43 56 l
adc1413d_ser all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 6 ? 8 june 2011 39 of 43 nxp semiconductors adc1413d series dual 14-bit adc; serial jesd204a interface 13. abbreviations table 54. abbreviations acronym description adc analog-to-digital converter dcs duty cycle stabilizer esd electrostatic discharge if intermediate frequency imd intermodulation distortion lsb least significant bit lvcmos low voltage complementary metal oxide semiconductor lvpecl low-voltage positive emitter-coupled logic msb most significant bit otr out-of-range prbs pseudo-random binary sequence sfdr spurious-free dynamic range snr signal-to-noise ratio spi serial peripheral interface tx transmitter
adc1413d_ser all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 6 ? 8 june 2011 40 of 43 nxp semiconductors adc1413d series dual 14-bit adc; serial jesd204a interface 14. revision history table 55. revision history document id release date data sheet status change notice supersedes adc1413d_ser v.6 20110608 product data sheet - adc1413d_ser v.5 modifications: ? section 10.2 ? clock and digital output timing ? has been updated. adc1413d_ser v.5 20110209 product data sheet - adc1413d_ser v.4 adc1413d_ser v.4 20100423 preliminary data sheet - adc1413d_ser v.3 adc1413d_ser v.3 20100412 objective data sheet - adc1413d065_080_105_125_2 adc1413d065_080_105_125_2 20090604 objective data sheet - adc1413d065_080_105_125_1 adc1413d065_080_105_125_1 20090528 objective data sheet - -
adc1413d_ser all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 6 ? 8 june 2011 41 of 43 nxp semiconductors adc1413d series dual 14-bit adc; serial jesd204a interface 15. legal information 15.1 data sheet status [1] please consult the most recently issued document before initiating or completing a design. [2] the term ?short data sheet? is explained in section ?definitions?. [3] the product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple device s. the latest product status information is available on the internet at url http://www.nxp.com . 15.2 definitions draft ? the document is a draft versi on only. the content is still under internal review and subject to formal approval, which may result in modifications or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall hav e no liability for the consequences of use of such information. short data sheet ? a short data sheet is an extract from a full data sheet with the same product type number(s) and title. a short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. for detailed and full information see the relevant full data sheet, which is available on request vi a the local nxp semiconductors sales office. in case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. product specification ? the information and data provided in a product data sheet shall define the specification of the product as agreed between nxp semiconductors and its customer , unless nxp semiconductors and customer have explicitly agreed otherwis e in writing. in no event however, shall an agreement be valid in which the nxp semiconductors product is deemed to offer functions and qualities beyond those described in the product data sheet. 15.3 disclaimers limited warranty and liability ? information in this document is believed to be accurate and reliable. however, nxp semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. in no event shall nxp semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interrupt ion, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. notwithstanding any damages that customer might incur for any reason whatsoever, nxp semiconductors? aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the terms and conditions of commercial sale of nxp semiconductors. right to make changes ? nxp semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. this document supersedes and replaces all information supplied prior to the publication hereof. suitability for use ? nxp semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an nxp semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. nxp semiconductors accepts no liability for inclusion and/or use of nxp semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer?s own risk. applications ? applications that are described herein for any of these products are for illustrative purpos es only. nxp semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. customers are responsible for the design and operation of their applications and products using nxp semiconductors products, and nxp semiconductors accepts no liability for any assistance with applications or customer product design. it is customer?s sole responsibility to determine whether the nxp semiconductors product is suitable and fit for the customer?s applications and products planned, as well as fo r the planned application and use of customer?s third party customer(s). customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. nxp semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer?s applications or products, or the application or use by customer?s third party customer(s). customer is responsible for doing all necessary testing for the customer?s applic ations and products using nxp semiconductors products in order to av oid a default of the applications and the products or of the application or use by customer?s third party customer(s). nxp does not accept any liability in this respect. limiting values ? stress above one or more limiting values (as defined in the absolute maximum ratings system of iec 60134) will cause permanent damage to the device. limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the recommended operating conditions section (if present) or the characteristics sections of this document is not warranted. constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. terms and conditions of commercial sale ? nxp semiconductors products are sold subject to the gener al terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms , unless otherwise agreed in a valid written individual agreement. in case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. nxp semiconductors hereby expressly objects to applying the customer?s general terms and conditions with regard to the purchase of nxp semiconducto rs products by customer. no offer to sell or license ? nothing in this document may be interpreted or construed as an offer to sell products t hat is open for acceptance or the grant, conveyance or implication of any lic ense under any copyrights, patents or other industrial or intellectual property rights. export control ? this document as well as the item(s) described herein may be subject to export control regulations. export might require a prior authorization from national authorities. document status [1] [2] product status [3] definition objective [short] data sheet development this document contains data from the objecti ve specification for product development. preliminary [short] data sheet qualification this document contains data from the preliminary specification. product [short] data sheet production this docu ment contains the product specification.
adc1413d_ser all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 6 ? 8 june 2011 42 of 43 nxp semiconductors adc1413d series dual 14-bit adc; serial jesd204a interface non-automotive qualified products ? unless this data sheet expressly states that this specific nxp semicon ductors product is automotive qualified, the product is not suitable for automotive use. it is neither qualified nor tested in accordance with automotive testing or application requirements. nxp semiconductors accepts no liabili ty for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. in the event that customer uses t he product for design-in and use in automotive applications to automotive s pecifications and standards, customer (a) shall use the product without nxp semiconductors? warranty of the product for such automotive applicat ions, use and specifications, and (b) whenever customer uses the product for automotive applications beyond nxp semiconductors? specifications such use shall be solely at customer?s own risk, and (c) customer fully indemnifies nxp semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive app lications beyond nxp semiconductors? standard warranty and nxp semiconduct ors? product specifications. 15.4 trademarks notice: all referenced brands, produc t names, service names and trademarks are the property of their respective owners. 16. contact information for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com
nxp semiconductors adc1413d series dual 14-bit adc; serial jesd204a interface ? nxp b.v. 2011. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please se nd an email to: salesaddresses@nxp.com date of release: 8 june 2011 document identifier: adc1413d_ser please be aware that important notices concerning this document and the product(s) described herein, have been included in section ?legal information?. 17. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4 ordering information . . . . . . . . . . . . . . . . . . . . . 2 5 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 pinning information . . . . . . . . . . . . . . . . . . . . . . 4 6.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 7 limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 6 8 thermal characteristics . . . . . . . . . . . . . . . . . . 6 9 static characteristics. . . . . . . . . . . . . . . . . . . . . 7 10 dynamic characteristics . . . . . . . . . . . . . . . . . 10 10.1 dynamic characteristics . . . . . . . . . . . . . . . . . 10 10.2 clock and digital output timing . . . . . . . . . . . . 11 10.3 serial output timing . . . . . . . . . . . . . . . . . . . . . 12 10.4 spi timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 11 application information. . . . . . . . . . . . . . . . . . 14 11.1 analog inputs . . . . . . . . . . . . . . . . . . . . . . . . . 14 11.1.1 input stage description . . . . . . . . . . . . . . . . . . 14 11.1.2 anti-kickback circuitry . . . . . . . . . . . . . . . . . . . 15 11.1.3 transformer . . . . . . . . . . . . . . . . . . . . . . . . . . 15 11.2 system reference and power management . . 16 11.2.1 internal/external reference . . . . . . . . . . . . . . . 16 11.2.2 programmable full-scale . . . . . . . . . . . . . . . . . 18 11.2.3 common-mode output voltage (v o(cm) ) . . . . . 19 11.2.4 biasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 11.3 clock input . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 11.3.1 drive modes . . . . . . . . . . . . . . . . . . . . . . . . . . 19 11.3.2 equivalent input circuit . . . . . . . . . . . . . . . . . . 20 11.3.3 duty cycle stabilizer . . . . . . . . . . . . . . . . . . . . 21 11.3.4 clock input divider . . . . . . . . . . . . . . . . . . . . . 21 11.4 digital outputs . . . . . . . . . . . . . . . . . . . . . . . . . 21 11.4.1 serial output equivalent circuit . . . . . . . . . . . . 21 11.5 jesd204a serializer. . . . . . . . . . . . . . . . . . . . 22 11.5.1 digital jesd204a formatter . . . . . . . . . . . . . . 22 11.5.2 adc core output codes versus input voltage . 23 11.6 serial peripheral interfac e (spi) . . . . . . . . . . . 24 11.6.1 register description . . . . . . . . . . . . . . . . . . . . 24 11.6.2 channel control . . . . . . . . . . . . . . . . . . . . . . . 25 11.6.3 register description . . . . . . . . . . . . . . . . . . . . 28 11.6.3.1 adc control registers . . . . . . . . . . . . . . . . . . 28 11.6.4 jesd204a digital control registers . . . . . . . . . 30 12 package outline . . . . . . . . . . . . . . . . . . . . . . . . 38 13 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 39 14 revision history . . . . . . . . . . . . . . . . . . . . . . . . 40 15 legal information . . . . . . . . . . . . . . . . . . . . . . 41 15.1 data sheet status . . . . . . . . . . . . . . . . . . . . . . 41 15.2 definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 15.3 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 41 15.4 trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 42 16 contact information . . . . . . . . . . . . . . . . . . . . 42 17 contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

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